MCMC Order-Graph Sampler Kernel

(about this photo)

This picture captures the single-FPGA MCMC Order-Graph Sampler circa Spring 2010. The design is broken into four parts: the scoring network or MSU (shown as red-blue box pairs), and three control blocks: the MCMC Controller (or MCU), PLiN, and RCBIOS (each shown as 'B', 'I', 'O' - respectively). The MCU can be thought of as the 'host thread' or controller while the MSU can be thought of as an FPGA-optimized data parallel accelerator. PLiN ('Platform Interconnect') is a cross-FPGA mesh network designed for use on the BEE3 platform. RCBIOS ('Reconfigurable Basic I/O System') is a hardware-software bit-banging stack used for system initialization and collecting results.

After pushing the kernel through the FPGA CAD flow, it looks like the following on a Virtex-5 LX155T FPGA:

I have adjusted the floorplan colors so that you can see a direct correspondance between the abstract diagram and the resulting implementation.